~~NOTOC~~
====== CSE4210 Architecture and Hardware for Digital Signal Processing  ======

===== Description  =====

The field of DSP (digital signal processing)is driven by two major forces, advances in DSP algorithms, and advances in VLSI technology that implements those algorithms. This course addresses the methodologies used to design custom or semi-custom VLSI circuits for DSP applications. Several techniques, such as pipelining, retiming, parallel processing, and folding, are introduced for speed enhancement, area reduction, and power saving. 

===== Learning Outcomes ======

Upon completion of the course, students should be able to:

  - map a DSP algorithm to a graphical representation and determine its fundamental lower bound on the achievable iteration or sampling period;
  - use pipelining, retiming, and parallel processing to improve the performance of a DSP implementation;
  - use folding technique to reduce silicon area in a DSP implementation;
  - assess alternative architectures based on a given set of design specifications;
  - implement a DSP algorithm based on an optimized architecture.

===== Instructor & Office Hours =====

  * Professor Peter Lian - peterlian AT cse DOT yorku DOT ca, [[http://www.cse.yorku.ca/cspeople/faculty/peterlian/index.html]]
  * Office Hours: Wednesday 11:00 - 12:30 or by appointment
  * Office location: 1012C Lassonde Building


===== Lecture and Lab Times =====

  * Lectures: Monday and Wednesday, 13:00 - 14:30, SC 219
  * Labs: Tuesday 11:30 - 13:30 LAS 3057

===== Teaching Assistant =====
  * Mr. Mingfei Wang, email: mingfei AT cse DOT yorku DOT ca
  * Office hour: Every Tuesday from 16:3-18:00 at Room 114 of Farquharson Building