Write a cache simulator (CacheSim) to simulate a cache. The simulator should be able to simulate up to 64KB cache. The simulator should run as CacheSim size in KB [flags], the flags are shown below

The memory is byte addressable with word access, words are 4 bytes

1. -a followed by the associativity (from 1 to 8), default is 1
2. -b block size in bytes, default is 32
3. -r followed bu U (unified) or S (split), default is unified
4. -f trace memory file name

For example

CachSim 32 -a 4 -b 16 -r U

The input t the simulator is a memory trace file. The file consists of lines, each line contains an integer i, followed by a 32-bit hex number. The hex number is the memory address, the integer i is

• 0 → data load
• 1 → data store
• 2 → instruction load

I will post shortly test trace files to check your code

Due date Friday Oct 14 MONDAY Oct 17

Here is the correct trace file for a direct mapped 16KB cache with 32 B cache block the number of misses is 25.

for 2-way set associative the misses are also 25

you can submit it to a2

submit 4201 a2 yourfile

a bigger trace file is here tex.txt